GOA circuit and display panel
US11521553B2 · kind B2 · utility
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10Claims
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Assignee
Inventor
Key dates
| Filing date | Jul 10, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Oct 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/045
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A GOA circuit and a display panel are provided. The GOA circuit and the display panel decrease thin film transistors required by an inverter in a circuit structure. A thin film transistor number is decreased, and an area occupied by a GOA space can be effectively decreased, which facilitates decreasing of border sizes of panels. Gates of thin film transistors of the GOA circuit are controlled by clock signals that have not been attenuated, which can prevent failure resulting from an attenuated cascaded signal caused by threshold voltage drifting of thin film transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.