Write circuit of memory device
US11521662B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 13, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes memory banks, a first pair of write data wirings, a second pair of write data wirings and a global write circuit. The first pair of write data wirings is connected to a first group among the memory banks. The second pair of write data wirings is connected to a second group among the memory banks. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal transmitted to the first group among the memory banks through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal transmitted to the second group among the memory banks through the second pair of write data wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.