Gate etch back with reduced loading effect
US11522065B2 · kind B2 · utility
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2References
20Claims
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Assignee
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Key dates
| Filing date | Mar 19, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jun 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.