Method and procedure for miniaturing a multi-layer PCB
US11523502B2 · kind B2 · utility
2Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | May 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09327
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include a plurality of layers that include a plurality of signal layers, a plurality of ground plane layers, a plurality of inner signal layers, and a single core substrate layer. Each layer in the plurality of layers may be separated from every other layer in the plurality of layers by at least one prepreg substrate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.