Programmable delay line with glitch suppression
US11526153B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2020 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Nov 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.