Multi-chip processing system and method for adding routing path information into headers of packets
US11526460B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Packet routing within a multi-chip processing system is shown. A first chip has a first interconnect bus, and a first microprocessor coupled to the first interconnect bus. The first interconnect bus has a first routing register. When the first microprocessor operates the first chip as a source node to output a packet to be transferred to a destination node, routing information indicating a routing path from the source node to the destination node is written into the first routing register and then loaded from the first routing register to a header of the packet. While being transferred within the multi-chip processing system from the source node to the destination node, the packet is guided along the routing path indicated in the routing information carried in the header of the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.