Enumerating coverage based on an architectural specification
US11526643B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Formal verification methods are used to solve a valid model of a design-under-test (DUT) to enumerate valid coverage points based on an architectural specification of the DUT. A formal solver can be queried to solve for valid solutions by crossing one or more fields of a variable. After each valid solve, values of the variable fields can be recorded and a count for number of valid solutions can be incremented. A new rule can be added to the solving process after each valid solve to invalidate the recorded values of the variable fields for subsequent solves. The count for the number of valid solutions can provide a running total of the valid solutions found for the query. Results of the query can be processed to convert the recorded values to provide the enumerated coverage points. The enumerated coverage points can be converted to test cases for running simulations on the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.