TEG test key of array substrate and display panel
US11527450B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Dec 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test element group (TEG) test key of an array substrate and a display panel thereof are provided. The TEG test key of the array substrate includes a glass substrate, a multi-buffer layer, an active layer, a gate insulating layer, a gate electrode layer, an interlayer insulating layer, a source and drain electrode layer, and an organic planarization layer stacked in sequence. The TEG test key of the array substrate is defined with two test zones and a connecting zone, and each test zone is provided with a groove exposing the gate electrode layer. The gate electrode layer in the test zones is electrically connected to the source and drain electrode layer in the connecting zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.