Interface for revision-limited memory
US11528126B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
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Key dates
| Filing date | Feb 16, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Feb 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.