Integrated circuit with clock gapping
US11531366B2 · kind B2 · utility
0Cited by
5References
20Claims
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Key dates
| Filing date | Jan 21, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | May 20, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.