Integrated circuit device, system-on-chip including the same, and packet processing method
US11531489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Feb 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.