Processing apparatus and processing method with dynamically configurable operation bit width
US11531540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2018 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jun 12, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.