Techniques to generate execution schedules from neural network computation graphs
US11531565B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Feb 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for a compiler scheduling algorithm/routine that utilizes backtracking to generate an execution schedule for a neural network computation graph using a neural network compiler intermediate representation of hardware synchronization counters. The hardware synchronization counters may be referred to as physical barriers, hardware (HW) barriers, or barriers and their intermediate representations may be referred to as barrier tasks or barriers. Backtracking is utilized to prevent an available number of hardware barriers from being exceeded during performance of an execution schedule. An execution schedule may be a computation workload schedule for neural network inference applications. An execution schedule may also be a first in first out (FIFO) schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.