Error correction circuit and method for operating the same
US11531588B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 21, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Sep 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3723
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.