Stacked neuromorphic devices and neuromorphic computing systems
US11531871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jun 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.