Convolution acceleration with embedded vector decompression
US11531873B2 · kind B2 · utility
5Cited by
28References
32Claims
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Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Mar 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.