Semiconductor memory device
US11532363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.