Array substrate and method of manufacturing the same, and display apparatus
US11532645B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Dec 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a base, a plurality of thin film transistors, a passivation layer, at least one reflective electrode, and at least one first connecting electrode. The array substrate has a display area. The thin film transistors are disposed in the display area on the base. The passivation layer covers the thin film transistors, and has at least one first via hole in the display area. The reflective electrode is disposed on a surface of the passivation layer facing away from the base, and is disposed in the display area and uncovers the first via hole. The first connecting electrode is disposed on a side of the reflective electrode away from the base. Each first connecting electrode is connected to a corresponding reflective electrode, and is connected to a source or a drain of a corresponding thin film transistor through a corresponding first via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.