Method of manufacturing array substrate, and array substrate
US11537016B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 13, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Apr 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/133345
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.