Emulation test system for flash translation layer and method thereof
US11537329B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.