Handling memory requests
US11537427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jan 12, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.