Effective PCIe utilization by PCIe TLP coalescing
US11537524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.