High throughput, low power, high parity architecture for database SSD
US11537534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | May 10, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.