Acceleration of data between a network and local I/O in a NUMA system
US11537539B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Oct 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system includes a central processing unit (CPU) including semiconductor dies, wherein each semiconductor die includes processing cores. The system includes a multi-host network interface card (NIC). The NIC includes an external connection interface circuit and CPU interface circuits. The NIC is coupled to an external data source through the external connection interface circuit and to each the semiconductor dies through a respective CPU interface circuit. The NIC is configured to receive data from the external data source for a different peripherals separately connected to semiconductor dies, and route the data for peripherals through respective CPU interface circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.