Direct memory access circuitry and method
US11537542B1 · kind B1 · utility
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14Claims
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Key dates
| Filing date | Jan 27, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jun 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.