Deadlock condition avoidance in a data processing system with a shared slave
US11537545B2 · kind B2 · utility
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5References
19Claims
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Key dates
| Filing date | Jul 31, 2020 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Aug 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for controlling deadlock in a processing system includes asserting a deadlock condition indicator when a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and an empty indicator indicates a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device. When the deadlock condition indicator is asserted, action can be taken by the processing system to eliminate the deadlock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.