Patent · US Active

Secure peripheral interconnect

US11537762B2 · kind B2 · utility

0Cited by

4References

10Claims

0Family size

Assignee

Nordic Semiconductor ASA · NO

Inventors

Ronan Barzic · Trondheim, NO
Anders Nore · Trondheim, NO
Vegard Endresen · Trondheim, NO

Key dates

Filing date	Jun 26, 2019
Grant date	Dec 27, 2022
Priority date	—
Expiry date	Jun 26, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/70
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated-circuit device comprises a bus system connected to a processor, a plurality of peripherals, each connected to the bus system, hardware filter logic; and a peripheral interconnect system, separate from the bus system and connected to the peripherals. For each peripheral, the hardware filter logic stores a respective value determining whether the peripheral is in a secure state. The peripheral interconnect system provides a set of one or more channels for signalling events between peripherals. At least one channel is a secure channel or is configurable to be a secure channel. The peripheral interconnect system is configured to allow an event signal from a peripheral in the secure state to be sent over a secure channel and to prevent an event signal from a peripheral that is not in the secure state from being sent over the secure channel.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.