Systems and methods for integrated circuit layout
US11537773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.