Low spike count ring buffer mechanism on neuromorphic hardware
US11537855B2 · kind B2 · utility
0Cited by
7References
21Claims
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Key dates
| Filing date | Sep 24, 2018 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | May 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C21/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.
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