Reduction mode of planar engine in neural processor
US11537864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Mar 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a neural processor that includes one or more neural engine circuits and planar engine circuits. The neural engine circuits can perform convolution operations of input data with one or more kernels to generate outputs. The planar engine circuit is coupled to the plurality of neural engine circuits. A planar engine circuit can be configured to multiple modes. In a reduction mode, the planar engine circuit may process values arranged in one or more dimensions of input to generate a reduced value. The reduced values across multiple input data may be accumulated. The planar engine circuit may program a filter circuit as a reduction tree to gradually reduce the data into a reduced value. The reduction operation reduces the size of one or more dimensions of a tensor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.