System and method for latency-aware mapping of quantum circuits to quantum chips
US11537925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quantum circuit generator for a quantum computer includes a controller; and a plurality of analog conversion units (ACUs) operatively connected to the controller, each ACU being operatively connected to a corresponding qubit of a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control a quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits of the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits being mapped by the controller and based on latency of the generated quantum circuit so that the generated quantum circuit has a latency less than a threshold latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.