Semiconductor device, semiconductor chip and method of manufacturing semiconductor device
US11538729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Sep 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.