Power semiconductor package with highly reliable chip topside
US11538734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jan 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor module includes a substrate with a metallization layer and a power semiconductor chip bonded to the metallization layer of the substrate. A metallic plate has a first surface bonded to a surface of the power semiconductor chip opposite to the substrate. The metallic plate has a central part and a border that are both bonded to the power semiconductor chip. The border of the metallic plate is structured in such a way that the metallic plate has less metal material per volume at the border as compared to the central part of the metallic plate. Metallic interconnection elements are bonded to a second surface of the metallic plate at the central part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.