Isolated transformer with integrated shield topology for reduced EMI
US11538766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2020 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Feb 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.