Power manager circuit and electronic device for detecting internal errors
US11543841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jun 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3206
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.