Gate driver circuit for reducing deadtime inefficiencies
US11543846B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.