Semiconductor storage device, memory system, and method
US11544209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Aug 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.