System and method of power management in memory design
US11545192B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.