Address latch comprising intermediate latch circuit that latches the address data latched by the write latch circuit, display device and address latching method
US11545197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jan 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address latch, a display device, and an address latching method are disclosed. The address latch includes a write control circuit, a write latch circuit, a latch control circuit, an intermediate latch circuit, and an output latch circuit. The write latch circuit is configured to latch an address data in response to N write control signals generated by the write control circuit, N data bits of the address data are divided into (M−1) data bit groups; the latch control circuit is configured to sequentially generate M latch control signals; the intermediate latch circuit is configured to, in response to first to (M−1)-th latch control signals, latch first to (M−1)-th data bit groups latched by the write latch circuit in a time-division manner; and the output latch circuit is configured to output the address data latched by the intermediate latch circuit in response to an M-th latch control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.