Manufacturer self-test for solid-state drives
US11545230B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2019 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Oct 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.