Semiconductor package
US11545458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Apr 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.