Clock and data recovery for multi-phase, multi-level encoding
US11545980B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4923
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.