Type-I PLLs for phase-controlled applications
US11545982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Mar 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.