Patent · US Active

Test method for a system on chip and a test system for the system on chip

US11549979B2 · kind B2 · utility

0Cited by
6References
20Claims
0Family size

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Key dates

Filing dateSep 21, 2021
Grant dateJan 10, 2023
Priority date—
Expiry dateSep 21, 2041

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2884
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A test method for a system on chip, the test method including: receiving a system on chip including a plurality of blocks; booting up the system on chip; storing input values that are input to each of the plurality of blocks, while booting up the system on chip; and performing a test on a first block among the plurality of blocks, wherein performing the test on the first block includes: disabling components of each of the plurality of blocks except the first block, and inputting a first input value to the first block to initialize the first block, wherein the first input value is one of the stored input values that was input to the first block while booting-up the system on chip.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.