Merged machine-level intermediate representation optimizations
US11550554B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer device is provided that includes a processor configured to receive a source code for a program including at least two code files, and process the source code for the program to generate a machine-level code file for each of the at least two code files of the source code. The processor is further configured to generate control flow graph data for each machine-level code file generated for the at least two code files of the source code, generate a machine-level intermediate representation for each machine-level code file using a machine-level code file and the generated control flow graph data for that machine-level code file, merge the machine-level intermediate representations into a merged machine-level intermediate representation, and perform machine-level optimizations on the merged machine-level intermediate representation and output an optimized merged machine-level intermediate representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.