Memory circuit for halting a program counter while fetching an instruction sequence from memory
US11550577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2019 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | May 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/9024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.