Neural network architecture using control logic determining convolution operation sequence
US11551065B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Nov 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising a plurality of convolution engines each operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of a filter with a respective data value of a data window; control logic configured to: receive configuration information identifying a set of filters for operation on a set of data windows at the plurality of convolution engines; determine, using the configuration information, a sequence of convolution operations for evaluation at the multiplication logic; in accordance with the determined sequence of convolution operations, request weights and data values for at least partially applying a filter to a data window; and cause the multiplication logic to combine the weights with their respective data values; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.