Memory device and an operating method thereof
US11551729B2 · kind B2 · utility
1Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.