Patent · US Active

Voltage offset for compute-in-memory architecture

US11551759B2 · kind B2 · utility

1Cited by

2References

15Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Edward Harrison Teague · San Diego, US
Zhongze Wang · San Diego, US
Max Welling · Bussum, NL

Key dates

Filing date	Apr 30, 2020
Grant date	Jan 10, 2023
Priority date	—
Expiry date	Apr 30, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06N3/045
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.