System and method for detecting and repairing defective memory cells
US11551778B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
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Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a memory module that enables online repair of defective memory cells. The memory module includes a memory array storing data, a self-test controller coupled to the memory array and configured to perform a self-test on a region within the memory array without interrupting operations of the memory module, and a memory-repair module configured to repair a defective memory cell identified by the self-test controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.